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rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ad5305/ad5315/ad5325 * 2.5 v to 5.5 v, 500 a, 2-wire interface quad voltage output, 8-/10-/12-bit dacs * protected by u.s.patent no. 5,969,657and 5,684,481. features ad5305: 4 buffered 8-bit dacs in 10-lead msop a version: 1 lsb inl, b version: 0.625 lsb inl ad5315: 4 buffered 10-bit dacs in 10-lead msop a version: 4 lsb inl, b version: 2.5 lsb inl ad5325: 4 buffered 12-bit dacs in 10-lead msop a version: 16 lsb inl, b version: 10 lsb inl low power operation: 500 a @ 3 v, 600 a @ 5 v 2-wire (i 2 c compatible) serial interface 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 80 na @ 3 v, 200 na @ 5 v three power-down modes double-buffered input logic output range: 0 v to v ref power-on reset to 0 v simultaneous update of outputs ( ldac function) software clear facility data readback facility on-chip rail-to-rail output buffer ampli?rs temperature range ?0 c to +105 c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control functional block diagram input register v out a buffer dac register string dac a v dd ref in gnd ad5305/ad5315/ad5325 input register v out b buffer dac register input register v out c buffer dac register input register v out d buffer dac register power-on reset sda scl a0 interface logic power-down logic ldac string dac b string dac c string dac d general description the ad5305/ad5315/ad5325 are quad 8-, 10-, and 12-bit buffered voltage output dacs in a 10-lead msop that operate from a single 2.5 v to 5.5 v supply, consuming 500 a at 3 v. their on-chip output ampli?rs allow rail-to-rail output swing with a slew rate of 0.7 v/ s. a 2-wire serial interface, which operates at clock rates up to 400 khz, is used. this interface is smbus compatible at v dd < 3.6 v. multiple devices can be placed on the same bus. the references for the four dacs are derived from one reference pin. the outputs of all dacs may be updated simultaneously using the software ldac function. the parts incorporate a power-on reset circuit, which ensures that the dac outputs power up to 0 v and remain there until a valid write takes place to the device. there is also a software clear function that resets all input and dac registers to 0 v. the parts contain a power-down feature that reduces the current consumption of the devices to 200 na @ 5 v (80 na @ 3 v). the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. the power consumption is 3 mw at 5 v, 1.5 mw at 3 v, reducing to 1 w in power-down mode.
rev. f e2e ad5305/ad5315/ad5325especifications (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specitcations t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments dc performance 3, 4 ad5305 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5315 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5325 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3% of fsr gain error 0.15 1 0.15 1% of fsr lower deadband 20 60 20 60 mv lower deadband exists only if offset error is negative. offset error drift 5 e12 e12 ppm of fsr/ c gain error drift 5 e5 e5 ppm of fsr/ c power supply rejection ratio 5 e60 e60 db v dd = 10% dc crosstalk 5 200 200 vr l = 2 k to gnd or v dd dac reference inputs 5 v ref input range 0.25 v dd 0.25 v dd v v ref input impedance 37 45 37 45 k normal operation >10 >10 m power-down mode reference feedthrough e90 e90 db frequency = 10 khz output characteristics 5 minimum output voltage 6 0.001 0.001 v this is a measure of the minimum and maximum drive capability maximum output voltage 6 v dd e 0.001 v dd e 0.001 v of the output ampliter. dc output impedance 0.5 0.5 short circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 s coming out of power-down mode. v dd = 5 v 55 s coming out of power-down mode. v dd = 3 v logic inputs (a0) 5 input current 1 1 a v il , input low voltage 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v v ih , input high voltage 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf logic inputs (scl, sda) 5 v ih , input high voltage 0.7 v dd v dd + 0.3 0.7 v dd v dd + 0.3 vs mbus compatible at v dd < 3.6 v v il , input low voltage e0.3 0.3 v dd e0.3 0.3 v dd vs mbus compatible at v dd < 3.6 v i in , input leakage current 1 1 a v hyst , input hysteresis 0.05 v dd 0.05 v dd v c in , input capacitance 8 8 pf glitch rejection 50 50 ns input tltering suppresses noise spikes of less than 50 ns. logic output (sda) 5 v ol , output low voltage 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma three-state leakage current 1 1 a three-state output capacitance 8 8 pf
rev. f ad5305/ad5315/ad5325 e3e ac characteristics 1 (v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specitcations t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 7 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 600 900 600 900 a v dd = 2.5 v to 3.6 v 500 700 500 700 a i dd (power-down mode) v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.2 1 0.2 1 ai dd = 4 a (max) during 0 readback on sda v dd = 2.5 v to 3.6 v 0.08 1 0.08 1 ai dd = 1.5 a (max) during 0 readback on sda notes 1 see the terminology section. 2 temperature range (a, b version): e40 c to +105 c; typical at +25 c. 3 dc specitcations tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5305 (code 8 to 248); ad5315 (code 28 to 995); ad5325 (code 115 to 3981). 5 guaranteed by design and characterization, not production tested. 6 for the ampliter output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. 7 i dd specitcation is valid for all dac codes. interface inactive. all dacs active and excluding load currents. specitcations subject to change without notice. a, b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5305 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5315 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5325 8 10 s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/ s major-code transition glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 1 nv-s digital crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p total harmonic distortion e70 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz notes 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range (a, b version): e40 c to +105 c; typical at +25 c. specitcations subject to change without notice.
rev. f e4e ad5305/ad5315/ad5325 timing characteristics 1, 2 (v dd = 2.5 v to 5.5 v; all specitcations t min to t max , unless otherwise noted.) limit at t min , t max parameter (a, b version) unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 250 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line notes 1 see figure 1. 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to v ih min of the scl signal) in order to bridge the undefined region of scl?s falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . specifications subject to change without notice. scl sda start condition t 9 t 3 t 4 t 6 t 2 t 5 t 7 t 8 t 1 t 4 t 11 t 10 repeated start condition stop condition figure 1. 2-wire serial interface timing diagram
rev. f ad5305/ad5315/ad5325 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5305/ad5315/ad5325 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v scl, sda to gnd . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v a0 to gnd . . . . . . . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v reference input voltage to gnd . . . . . e0.3 v to v dd + 0.3 v v out aed to gnd . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v operating temperature range industrial (a, b version) . . . . . . . . . . . . . . e40 c to +105 c storage temperature range . . . . . . . . . . . . . e65 c to +150 c junction temperature (t j m ax) . . . . . . . . . . . . . . . . . . . 150 c msop power dissipation . . . . . . . . . . . . . . . . . . . (t j m ax e t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 206 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 44 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c time at peak temperature . . . . . . . . . . . . . 10 sec to 40 sec notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specitcation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide model temperature range package description package option branding AD5305ARM e40 c to +105 c 10-lead msop rm-10 dea AD5305ARM-reel7 e40 c to +105 c 10-lead msop rm-10 dea ad5315arm e40 c to +105 c 10-lead msop rm-10 dfa ad5315arm-reel7 e40 c to +105 c 10-lead msop rm-10 dfa ad5325arm e40 c to +105 c 10-lead msop rm-10 dga ad5325arm-reel7 e40 c to +105 c 10-lead msop rm-10 dga ad5305brm e40 c to +105 c 10-lead msop rm-10 deb ad5305brm-reel e40 c to +105 c 10-lead msop rm-10 deb ad5305brm-reel7 e40 c to +105 c 10-lead msop rm-10 deb ad5315brm e40 c to +105 c 10-lead msop rm-10 dfb ad5315brm-reel e40 c to +105 c 10-lead msop rm-10 dfb ad5315brm-reel7 e40 c to +105 c 10-lead msop rm-10 dfb ad5325brm e40 c to +105 c 10-lead msop rm-10 dgb ad5325brm-reel e40 c to +105 c 10-lead msop rm-10 dgb ad5325brm-reel7 e40 c to +105 c 10-lead msop rm-10 dgb
rev. f e6e ad5305/ad5315/ad5325 pin configuration top view (not to scale) 10 9 8 7 6 1 2 3 4 5 v dd v out a gnd sda scl v out d ad5305/ ad5315/ ad5325 v out b v out c refin a0 pin function descriptions pin no. mnemonic function 1v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled to gnd. 2v out ab uffered analog output voltage from dac a. the output ampliter has rail-to-rail operation. 3v out bb uffered analog output voltage from dac b. the output ampliter has rail-to-rail operation. 4v out cb uffered analog output voltage from dac c. the output ampliter has rail-to-rail operation. 5 refin reference input pin for all four dacs. it has an input range from 0.25 v to v dd . 6v out db uffered analog output voltage from dac d. the output ampliter has rail-to-rail operation. 7g nd ground reference point for all circuitry on the part. 8 sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input shift register. it is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 scl serial clock line. this is used in conjunction with the sda line to clock data into or out of the 16-bit input shift register. clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface. 10 a0 address input. sets the least signitcant bit of the 7-bit slave address. terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer func tion. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specited differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output ampliter. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at mid scale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac out- put to the reference input when the dac output is not being updated. it is expressed in db.
rev. f ad5305/ad5315/ad5325 e7e major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specited as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00, or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being updated. it is specited in nv-s and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the ampliters within the dac have a tnite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is measured in db. actual ideal gain error plus offset error output voltage negative offset error dac code amplifier footroom (1mv) dead band codes negative offset error figure 2. transfer function with negative offset output voltage positive offset dac code gain error plus offset error actual ideal figure 3. transfer function with positive offset
rev. f e8e ad5305/ad5315/ad5325etypical performance characteristics code inl error (lsb) 1.0 0.5 e1.0 0 50 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v tpc 1. ad5305 typical inl plot code dnl error (lsb) 0.3 e0.3 050 250 100 150 200 e0.1 e0.2 0.2 0.1 0 t a = 25 c v dd = 5v tpc 4. ad5305 typical dnl plot v ref (v) error (lsb) 0.50 0.25 e0.50 01 5 234 0 e0.25 v dd = 5v t a = 25 c max inl max dnl min dnl min inl tpc 7. ad5305 inl and dnl error vs. v ref code inl error (lsb) 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v tpc 2. ad5315 typical inl plot code dnl error (lsb) 0.6 0.4 0 200 1000 400 600 800 e0.2 e0.6 0.2 0 e0.4 t a = 25 c v dd = 5v tpc 5. ad5315 typical dnl plot temperature ( c) error (lsb) 0.5 0.2 e0.5 40 0 40 0 e0.2 v dd = 5v v ref = 3v max inl 80 120 e0.4 e0.3 e0.1 0.1 0.3 0.4 max dnl min inl min dnl tpc 8. ad5305 inl and dnl error vs. temperature code inl error (lsb) 12 0 e4 e8 8 4 0 4000 1000 2000 3000 e12 t a = 25 c v dd = 5v tpc 3. ad5325 typical inl plot code dnl error (lsb) 0.5 2000 3000 4000 0 e1.0 1.0 e0.5 t a = 25 c v dd = 5v 1000 0 tpc 6. ad5325 typical dnl plot gain error temperature ( c) error (%) 1.0 0.5 e1.0 40 0 40 0 e0.5 v dd = 5v v ref = 2v offset error 80 120 tpc 9. ad5305 offset error and gain error vs. temperature
rev. f ad5305/ad5315/ad5325 e9e gain error v dd (v) error (%) 0.2 e0.6 01 3 0 e0.4 t a = 25 c v ref = 2v 46 e0.5 e0.3 e0.2 e0.1 0.1 25 offset error tpc 10. offset error and gain error vs. v dd v dd (v) i dd ( a) 600 0 500 100 200 300 400 2.5 3.0 4.0 4.5 5.5 3.5 5.0 +105 c 40 c +25 c tpc 13. supply current vs. supply voltage v out a 5s t a = 25 c v dd = 5v v ref = 5v ch1 ch2 scl ch1 1v, ch2 5v, time base = 1 s/div tpc 16. half-scale settling (1/4 to 3/4 scale code change) 5v source sink/source current (ma) v out (v) 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink tpc 11. v out source and sink current capability v dd (v) i dd ( a) 0.5 0 0.4 0.1 0.2 0.3 2.5 3.0 4.0 4.5 5.5 3.5 5.0 105 c 40 c 25 c tpc 14. power-down current vs. supply voltage v dd ch1 ch2 v out a ch1 2v, ch2 200mv, time base = 200 s/div 5s t a = 25 c v dd = 5v v ref = 2v tpc 17. power-on reset to 0 v code i dd ( a) 600 0 500 100 200 300 400 t a = 25 c v dd = 5v v ref =2v zero scale full scale tpc 12. supply current vs. dac code v logic (v) 750 450 0 550 650 i dd ( a) 1.0 2.0 3.0 4.0 5.0 t a = 25 c v dd = 5v v dd = 3v increasing decreasing tpc 15. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing v out a ch1 ch2 scl ch1 500mv, ch2 5v, time base = 1 s/div t a = 25 c v dd = 5v v ref = 2v tpc 18. exiting power-down to midscale
rev. f e10e ad5305/ad5315/ad5325 functional description the ad5305/ad5315/ad5325 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer ampliters and is written to via a 2-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer am pliters provide rail-to-rail output swing with a slew rate of 0.7 v/ s. the four dacs share a single reference input pin. the devices have three programmable power-down modes, in which all dacs may be turned off completely with a high impedance output, or the outputs may be pulled low by on-chip resistors. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer ampliter. the voltage at the refin pin provides the reference voltage for the dac. figure 4 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out ref n = 2 i dd ( a) frequency 300 350 600 400 450 500 550 v dd = 5v v dd = 3v tpc 19. i dd histogram with v dd = 3 v and v dd = 5 v v dd = 5v t a = 25 c v ref (v) full-scale error (v) 0.02 e0.02 01 3 0.01 e0.01 46 0 25 tpc 22. full-scale error vs. v ref 1 s/div 2.48 2.49 v out (v) 2.47 2.50 tpc 20. ad5325 major-code transition glitch energy 50ns/div 1mv/div tpc 23. dac-to-dac crosstalk frequency (hz) 10 e40 10 e20 e30 0 e10 db 100 1k 10k 100k 1m 10m e50 e60 tpc 21. multiplying bandwidth (small-signal frequency response) where d = decimal equivalent of the binary code, which is loaded to the dac register: 0e255 for ad5305 (8 bits) 0e1023 for ad5315 (10 bits) 0e4095 for ad5325 (12 bits) n = dac resolution input register refin output buffer amplifier v out a resistor string dac register figure 4. dac channel architecture
rev. f ad5305/ad5315/ad5325 e11e resistor string the resistor string section is shown in figure 5. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output ampliter. the voltage is tapped off by closing one of the switches connecting the string to the ampliter. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier figure 5. resistor string dac reference inputs there is a single reference input pin for the four dacs. the reference input is unbuffered. the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of any reference ampliter. it is recommended to use a buffered reference in the external circuit (e.g., ref192). the input impedance is typically 45 k . output ampliter the output buffer ampliter is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd when the reference is v dd . it is capable of driving a load of 2 k to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output ampliter can be seen in the plot in tpc 11. the slew rate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s. power-on reset the ad5305/ad5315/ad5325 are provided with a power-on reset function, so that they power up in a detned state. the power-on state is ? normal operation ? output voltage set to 0 v both input and dac registers are tlled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. serial interface the ad5305/ad5315/ad5325 are controlled via an i 2 c com patible serial bus. the dacs are connected to this bus as slave devices (i.e., no clock is generated by the ad5305/ad 5315/ ad5325 dacs). this interface is smbus compatible at v dd < 3.6 v. the ad5305/ad5315/ad5325 have a 7-bit slave address. the 6 msb are 000110 and the lsb is determined by the state of the a0 pin. the facility to make hardwired changes to a0 allows the user to use up to two of these devices on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address fol- lowed by an r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condi- tion is established. in write mode, the master will pull the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master will then bring the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. read/write sequence in the case of the ad5305/ad5315/ad5325, all write access sequences and most read sequences begin with the device ad dress (with r/ w = 0) followed by the pointer byte. this pointer byte specites the data format and determines which dac is being accessed in the subsequent read/write operation. (see figure 6.) in a write operation, the data follows immediately. in a read operation, the address is resent with r/ w = 1 and then the data is read back. however, it is also possible to perform a read operation by sending only the address with r/ w = 1. the previ ously loaded pointer settings are then used for the read- back operation. see figure 7 for a graphical explanation of the interface. dacd x x lsb msb dacc dacb daca 0 0 figure 6. pointer byte
rev. f ?2 ad5305/ad5315/ad5325 pointer byte bits the following is an explanation of the individual bits that make up the pointer byte. xd on? care bits. 0r eserved bits, must be set to 0. dacd 1: the following data bytes are for dac d. dacc 1: the following data bytes are for dac c. dacb 1: the following data bytes are for dac b. daca 1: the following data bytes are for dac a. input shift register the input shift register is 16 bits wide. data is loaded into the device as two data bytes on the serial data line, sda, under the control of the serial clock input, scl. the timing diagram for this operation is shown in figure 1. the two data bytes consist of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the ?st two bits loaded are pd1 and pd0 bits that control the mode of operation of the device. see the power-down modes section for a complete descrip tion. bit 13 is clr , bit 12 is ldac , and the remaining bits are left- justi?d dac data bits, starting with the msb. see figure 7. clr 0: all dac registers and input registers are ?led with zeros on completion of the write sequence. 1: normal operation. ldac 0: all four dac registers and, therefore, all dac outputs simultaneously updated on completion of the write sequence. 1: only addressed input register is updated. there is no change in the contents of the dac registers. default readback condition all pointer byte bits power up to 0. therefore, if the user ini tiates a readback without writing to the pointer byte ?st, no single dac channel has been speci?d. in this case, the default readback bits are all 0, except for the clr bit, which is a 1. multiple-dac write sequence because there are individual bits in the pointer byte for each dac, it is possible to write the same data and control bits to 2, 3, or 4 dacs simultaneously by setting the relevant bits to 1. multiple-dac readback sequence if the user attempts to read back data from more than one dac at a time, the part will read back the default, power-on reset conditions, i.e., all 0s except for clr , which is 1. pd0 clr ldac d7 d6 d5 d4 pd1 lsb msb 8-bit ad5305 pd0 clr ldac d9 d8 d7 d6 pd1 pd0 d11 d10 d9 d8 pd1 most significant data byte data bytes (write and readback) lsb msb 10-bit ad5315 lsb msb 12-bit ad5325 clr ldac least significant data byte d3 d2 d1 d0 0 0 0 0 d5 d4 d3 d2 d1 d0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb 8-bit ad5305 lsb msb 10-bit ad5315 lsb msb 12-bit ad5325 figure 7. data formats for write and readback
rev. f ad5305/ad5315/ad5325 ?3 write operation when writing to the ad5305/ad5315/ad5325 dacs, the user must begin with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the pointer byte, which is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 8. a stop condi- tion follows. most significant data byte least significant data byte 0 0011 a0 r/ w xx lsb ack by ad53x5 ack by ad53x5 msb address byte start cond by master scl sda scl sda msb lsb msb lsb ack by ad53x5 ack by ad53x5 stop cond by master pointer byte 0 figure 8. write sequence
rev. f ?4 ad5305/ad5315/ad5325 read operation when reading data back from the ad5305/ad5315/ad5325 dacs, the user begins with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. this address byte is usually followed by the pointer byte, which is also acknowledged by the dac. following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac indicating that it is prepared to transmit data. two bytes of data are then read from the dac, as shown in figure 9. a stop condition follows. however, if the master sends an ack and continues clocking scl (no stop is sent), the dac will retransmit the same two bytes of data on sda. this allows continuous readback of data from the selected dac register. alternatively, the user may send a start followed by the ad dress with r/ w = 1. in this case, the previously loaded pointer settings are used and readback of data can commence immediately. data byte least significant data byte 00 0 11 a0 r/ w xx lsb ack by ad53x5 scl sda start cond by master ack by ad53x5 msb scl sda 00 0 11 0 a0 r/ w msb lsb ack by master repeated start cond by master ack by ad53x5 address byte scl sda msb lsb no ack by master stop cond by master pointer byte address byte 0 note: data bytes are the same as those in the write sequence except that don? cares are read back as 0s. figure 9. readback sequence
rev. f ad5305/ad5315/ad5325 e15e double-buffered interface the ad5305/ad5315/ad5325 dacs have double-buffered interfaces consisting of two banks of registers?input registers and dac registers. the input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac register contains the digital code used by the resistor string. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and, there- fore, the input register may change state without affecting the contents of the dac register. however, when the ldac bit is set low, the dac register becomes transparent and the contents of the input register are transferred to it. this is useful if the user requires simultaneous updating of all dac outputs. the user may write to three of the input registers individually and then, by setting the ldac bit low when writing to the remaining dac input register, all outputs will update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since t he last time that ldac was brought low. normally, when ldac is brought low, the dac registers are tlled with the contents of the input registers. in the case of the ad5305/ad5315/ad 5325, the part will update the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down modes the ad5305/ad5315/ad5325 have very low power consump- tion, dissipating typically 1.5 mw with a 3 v supply and 3 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into one of three power-down modes, which are selected by bits 15 and 14 (pd1 and pd0) of the data byte. table i shows how the state of the bits corresponds to the mode of operation of the dac. table i. pd1/pd0 operating modes pd1 pd0 operating mode 00 normal operation 01 power-down (1 k load to gnd) 10 power-down (100 k load to gnd) 11 power-down (three-state output) when both bits are set to 0, the dac works normally with its normal power consumption of 600 a at 5 v. however, for the three power-down modes, the supply current falls to 200 na at 5 v (80 na at 3 v). not only does the supply current drop, but the output stage is also internally switched from the output of the ampliter to a resistor network of known values. this has an advantage in that the output impedance of the part is known while the part is in power-down mode and provides a detned input condition for whatever is connected to the output of the dac ampliter. there are three different options. the output is connected internally to gnd through either a 1 k resistor or a 100 k resistor, or it is left open-circuited (three-state). resistor tolerance = 20%. the output stage is illustrated in figure 10. amplifier power-down circuitry resistor network resistor string dac v out figure 10. output stage during power-down the bias generator, the output ampliters, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the dac registers are unchanged when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from the rising edge of the eighth scl pulse to when the output voltage deviates from its power-down voltage. see tpc 18 for a plot. applications typical application circuit the ad5305/ad5315/ad5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a txed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable exter- nal reference would be the ad589, a 1.23 v band gap reference. figure 11 shows a typical setup for the ad5305/ad5315/ad5325 when using an external reference. note that a0 can be high or low. ad5305/ ad5315/ ad5325 v out b v out d gnd sda serial interface v out ext ref 0.1 f v out a v out c refin ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v dd = 2.5v to 5.5v v in a0 10 f 1 f scl figure 11. ad5305/ad5315/ad5325 using external reference
rev. f e16e ad5305/ad5315/ad5325 if an output range of 0 v to v dd is required, the simplest solution is to connect the reference input to v dd . as this supply may not be very accurate and may be noisy, the ad5305/ad5315/ad5325 may be powered from the reference voltage; for example, using a 5 v reference such as the ref195. the ref195 will output a steady supply voltage for the ad5305/ad5315/ad5325. the typical current required from the ref195 is 600 a supply cur- rent and approximately 112 a into the reference input. this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is 712 4 5 10 2 70 avk ma + () = /. the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.4 ppm (27 v) for the 2.7 ma current drawn from it. this corresponds to a 0.0014 lsb error at eight bits and 0.022 lsb error at 12 bits. bipolar operation using the ad5305/ad5315/ad5325 the ad5305/ad5315/ad5325 have been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 12. this circuit will give an output voltage range of 5 v. rail-to-rail operation at the ampliter output is achievable using an ad820 or an op295 as the output ampliter. +5v e5v ad820/ op295 10 f 6v to 12v ad5305 0.1 f v dd v out a r1 = 10k 5v r2 = 10k refin a0 g nd v out v in ad1585 1 f +5v 2-wire serial interface scl sda v out c v out d v out b gnd figure 12. bipolar operation with the ad5305 the output voltage for any input code can be calculated as follows: v refin d 2 r1 r2 r1 refin r2 r1 out n = () + () ()

/ / e/ where d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v , r1 = r2 = 10 k : vd2 out n = () 10 5 /ev multiple devices on one bus figure 13 shows two ad5305 devices on the same serial bus. each has a different slave address since the state of the a0 pin is different. this allows each of eight dacs to be written to or read from independently. pull-up resistors micro- controller scl sda ad5305 a0 ad5305 scl sda a0 v dd figure 13. multiple ad5305 devices on one bus ad5305/ad5315/ad5325 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5305/ad5315/ad5325 is shown in figure 14. the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led will indicate the fail condition. similarly, dacs c and d can be used for window detection on a second v in signal. 1/2 ad5305/ ad5315/ ad5325 * v dd 5v v out a gnd refin v in pass/ fail 1/2 cmp04 1/6 74hc05 fail pass 1k 0.1 f10 f scl sda scl din 1k v out b v ref * additional pins omitted for clarity figure 14. window detection coarse and fine adjustment using the ad5305/ad5315/ ad5325 two of the dacs in the ad5305/ad5315/ad5325 can be paired together to form a coarse and tne adjustment function, as shown in figure 15. dac a is used to provide the coarse adjustment while dac b provides the tne adjustment. varying the ratio of r1 and r2 will change the relative effect of the coarse and tne adjustments. with the resistor values and exter- nal reference shown, the output ampliter has unity gain for the dac a output, so the output range is 0 v to 2.5 v e 1 lsb. for dac b, the ampliter has a gain of 7.6 10 e3 , giving dac b a range equal to 19 mv. similarly, dacs c and d can be paired together for coarse and tne adjustment. the circuit is shown with a 2.5 v reference, but reference volt- ages up to v dd may be used. the op amps indicated will allow a rail-to-rail output swing.
rev. f ad5305/ad5315/ad5325 e17e 1 f refin v dd gnd v out b 0.1 f 10 f v dd = 5v v out v in gnd ext ref ad820/ op295 5v r3 51.2k r4 390 ad780/ref192 with v dd = 5v v out a r1 390 r2 51.2k v out 1/2 ad5305/ ad5315/ ad5325 * * additional pins omitted for clarity figure 15. coarse/fine adjustment power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5305/ad5315/ad5325 is mounted should be designed so that the analog and digital sections are separated and contned to certain areas of the board. if the ad5305/ad5315/ad5325 is in a system where multiple devices require an agnd-to- dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5305/ad5315/ad5325 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5305/ad5315/ad5325 sh ould use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the sda and scl lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). avoid crossover of digital and analog signals. traces on oppo- site sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. f e18e ad5305/ad5315/ad5325 table ii. overview of all ad53xx serial devices no. of settling part no. resolution dacs dnl interface time ( s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 visit www.analog.com/support/standard_linear/selection_guides/ad53xx.html for more information. table iii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time ( s) additional pin functions package pins singles buf gain hben clr ?? ? ?? ?? ? ?? ? ? ? ?? ? ?? ? ?? ?? ?? ??
rev. f ad5305/ad5315/ad5325 e19e outline dimensions 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba
rev. f c00930??0/04(f) ?0 ad5305/ad5315/ad5325 revision history location page 10/04?ata sheet changed from rev. e to rev. f. changes to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to pointer byte bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8/03?ata sheet changed from rev. d to rev. e. added a version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to tpc 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 added octals section to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4/01?ata sheet changed from rev. c to rev. d. edit to features section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to right/left and double sections of pointer byte bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edit to input shift register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edit to multiple-dac readback sequence section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to write operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to read operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 edits to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 edits to power-down modes section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.

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